RISC-V Simulator

Editor Registers Memory Cache Stats

S No.	Statistic	Value
1	Total Cycles	None
2	Total Instructions	None
3	CPI	None
4	Data Transfer Instruction Count	None
5	ALU Instruction Count	None
6	Control Instruction Count	None
7	Stall/Bubble Count	None
8	Data Hazard Count	None
9	Control Hazard Count	None
10	Stalls due to data hazards	None
11	Stalls due to control hazards	None
12	Branch misprediction Count	None
13	Instruction Cache Access(s)	None
14	Instruction Cache Hits	None
15	Instruction Cache Miss(s)	None
16	Instruction Cache Cold Miss(s)	None
17	Instruction Cache Capacity Miss(s)	None
18	Instruction Cache Conflict Misses	None
19	Data Cache Access(s)	None
20	Data Cache Hits	None
21	Data Cache Miss(s)	None
22	Data Cache Cold Miss(s)	None
23	Data Cache Capacity Miss(s)	None
24	Data Cache Conflict Misses	None

Address	+0	+1	+2	+3
0x00000000	0x0	0x0	0x0	0x0

Reg No.	Value in Hex	Value in Decimal
0	None	None

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